1. Field of the Invention
The present invention relates to a test apparatus and a test method for testing electrical characteristics of a semiconductor chip after removing foreign matter from it.
2. Background Art
Japanese Laid-Open Patent Publication No. 2010-165943 discloses a technique for removing foreign matter adhering to a semiconductor wafer by blowing purge gas against the wafer. Japanese Laid-Open Patent Publication No. 2008-141135 discloses a technique for reducing the occurrence of foreign matter resulting from dicing a semiconductor wafer. In this technique, the metal electrodes on the semiconductor wafer are formed and processed so as not to cover the dicing lines, thereby minimizing the occurrence of foreign matter resulting from dicing.
It has been found in some cases that semiconductor chips have foreign matter adhering to sides thereof after they have been produced by dicing a wafer. If a semiconductor chip with such foreign matter is tested for electrical characteristics, the test results will be affected by the foreign matter, degrading the reliability of the test. Therefore, it is necessary to remove foreign matter (if any) from a semiconductor chip before testing its electrical characteristics.
However, it is difficult to remove foreign matter from a semiconductor chip (or wafer) merely by blowing purge gas against the chip, as in the technique disclosed in the above Patent Publication No. 2010-165943. Further, the technique disclosed in the above Patent Publication No. 2008-141135 requires the step of removing portions of the metal electrodes on the wafer so as to expose the dicing lines, resulting in increased manufacturing cost.